Master VHDL & Rust
Your North Star
A unified roadmap to keep you focused. Hardware meets automotive software. 175+ VHDL exercises and 16 weeks of Rust for automotive engineers.
by daudithemechanic
2026 Complete Learning Roadmap
15 chapters, 175+ exercises, and 5 capstone projects - from digital logic fundamentals to advanced VHDL design
Part 1: VHDL Fundamentals
40 pagesTopics Covered
- Boolean algebra refresher
- Logic gates and truth tables
- Combinational vs sequential circuits
- VHDL history and applications
- Simulation vs Synthesis concepts
All Exercises (8)
Truth Tables
Create truth tables for AND, OR, XOR, NAND, NOR, XNOR gates
Boolean Expressions
Derive Boolean expressions from given truth tables
Simplification
Simplify Boolean expressions using Boolean algebra
2-Input MUX Design
Design a 2-input multiplexer using basic gates
Tool Setup
Install GHDL and GTKWave on your system
First VHDL File
Write a simple VHDL file that compiles without errors
Waveform Diagram
Create a waveform diagram for a 4-input AND gate
Fundamentals Quiz
Quiz: 10 multiple choice questions on digital logic fundamentals
Topics Covered
- Entity-Architecture pair
- Port declarations and modes (in, out, inout, buffer)
- STD_LOGIC and STD_LOGIC_VECTOR
- BIT, BOOLEAN, INTEGER types
- Constants and signals
Exercise 2.1: Basic Entity Template
entity EXERCISE_2_1 is
port (
A, B : in std_logic;
F : out std_logic
);
end EXERCISE_2_1;All Exercises (10)
3-Input AND Gate
Create entity for a 3-input AND gate
4-Bit Input Entity
Design entity with 4-bit input and 1-bit output
8-Bit Data Bus
Declare signals for an 8-bit data bus
Constants
Create constants for clock period and delay values
2-Input OR Gate
Write architecture for a 2-input OR gate
Bidirectional Port
Design a 4-bit wide entity with bidirectional port
Type Conversion
Convert between std_logic_vector and integer types
Custom Package
Create a package with custom data types
Debug Exercise
Debug given code with 5 syntax errors
Data Types Quiz
Quiz on data types and port modes
Topics Covered
- Simple signal assignment
- Conditional signal assignment (when/else)
- Selected signal assignment (with/select)
- Generate statements
Exercise 3.3: 4-to-1 MUX using when/else
architecture BEHAVIORAL of MUX4 is
begin
Y <= A when SEL = "00" else
B when SEL = "01" else
C when SEL = "10" else
D;
end BEHAVIORAL;All Exercises (12)
2-to-1 MUX
Implement 2-to-1 MUX using when/else
3-to-8 Decoder
Design 3-to-8 decoder with with/select
4-to-1 MUX
Create 4-to-1 MUX using conditional assignment
Priority Encoder
Implement priority encoder (4-bit to 2-bit)
7-Segment Decoder
Design 7-segment decoder for hex digits 0-F
Barrel Shifter
Create barrel shifter using concurrent statements
Magnitude Comparator
Implement magnitude comparator (2-bit numbers)
Parity Generator
Design parity generator (even/odd selection)
Generate Statement
Use generate to create array of 8 AND gates
ALU Slice
Implement ALU slice with add/subtract operations
Debug Concurrent Code
Debug concurrent code (find 3 logical errors)
Mini-Project
Design a simple calculator (add/sub/and/or)
Design a simple calculator (add/sub/and/or)
Part 2: Combinational Logic Design
45 pagesTopics Covered
- Process statement structure
- Sensitivity lists
- Variable vs Signal assignment
- If-then-else statements
- Case statements
Exercise 4.5: Process with variables
process(A, B, C)
variable temp : std_logic_vector(3 downto 0);
begin
temp := A & B & C & '1';
if temp = "1111" then
OUTPUT <= '1';
else
OUTPUT <= '0';
end if;
end process;All Exercises (15)
D Flip-Flop
Write process for D flip-flop with async reset
8-to-1 MUX
Implement 8-to-1 MUX using case statement
BCD Converter
Design BCD to excess-3 converter using process
Variables Practice
Create process with variables for temporary calculations
Timing Comparison
Compare variable vs signal assignment timing
Full Adder
Implement full adder using process
Gray Code Converter
Design 4-bit binary to gray code converter
ALU Design
Create arithmetic logic unit (ALU) with 4 operations
Conditional Branches
Write process with multiple conditional branches
Look-up Table
Implement look-up table using case statement
Sensitivity List Debug
Debug process with incomplete sensitivity list
Hamming Encoder
Design Hamming code encoder (7,4)
Thermometer Code
Create process for thermometer code converter
Booth Multiplier
Implement booth multiplier (4x4 bits)
Mini-Project
Simple CPU control unit
Simple CPU control unit
Topics Covered
- Function declaration and usage
- Procedure definition
- Pure vs impure functions
- Parameter modes (in, out, inout)
- Return statements
Exercise 5.2: Function for parity calculation
function calc_parity(data : std_logic_vector) return std_logic is
variable parity : std_logic := '0';
begin
for i in data'range loop
parity := parity xor data(i);
end loop;
return parity;
end function;All Exercises (10)
Integer to Binary
Write function to convert integer to binary vector
Parity Function
Create function for even parity calculation
Memory Init Procedure
Design procedure to initialize memory array
Maximum Function
Implement function for finding maximum of 3 numbers
Out Parameters
Create procedure with out parameters
CRC Calculation
Write function for CRC calculation (simple)
Bit Reversal
Design procedure for bit reversal
Function Overload
Implement function overload for different types
Reusable Package
Create package with reusable functions
Mini-Project
Math operations package
Math operations package
Topics Covered
- Package declaration and body
- Library and use clauses
- Standard packages (std_logic_1164, numeric_std)
- User-defined packages
- Component declarations
All Exercises (8)
Custom Types Package
Create package with custom types and constants
Conversion Package
Design package for conversion functions
Component Package
Implement package with component declarations
Numeric Std Practice
Use numeric_std for arithmetic operations
Math Package
Create math package with add/sub/mult functions
Testbench Utilities
Design testbench utilities package
UART Constants
Implement package for UART constants
Mini-Project
Complete design using packages
Complete design using packages
Part 3: Sequential Logic Design
55 pagesTopics Covered
- D, T, JK, SR flip-flops
- Synchronous vs asynchronous reset
- Enable signals
- Register files
- Clocking methodologies
Exercise 7.3: D-FF with async reset and enable
process(clk, reset)
begin
if reset = '1' then
Q <= '0';
elsif rising_edge(clk) then
if enable = '1' then
Q <= D;
end if;
end if;
end process;All Exercises (15)
Sync Reset D-FF
Design D flip-flop with synchronous reset
T Flip-Flop
Implement T flip-flop from D flip-flop
D-FF with Enable
Create D-FF with async reset and enable
4-Bit Register
Design 4-bit register with parallel load
Universal Shift Register
Implement universal shift register
Register File
Create 8-bit register file (4 registers)
JK Flip-Flop
Design JK flip-flop with preset and clear
Ripple Counter
Implement ripple counter using T flip-flops
Tri-State Register
Create register with tri-state output
Up/Down Counter
Design synchronous up/down counter
Johnson Counter
Implement Johnson counter
FIFO Buffer
Create FIFO buffer (4x8 bits)
Debounce Circuit
Design debounce circuit for push button
Clock Divider
Implement clock divider (divide by 2, 4, 8)
Mini-Project
8-bit accumulator
8-bit accumulator
Topics Covered
- Moore vs Mealy machines
- State encoding (binary, one-hot, gray)
- FSM design methodology
- State transition diagrams
- Output logic
Exercise 8.5: Sequence detector FSM
type STATE_TYPE is (S0, S1, S2, S3, S4);
signal current_state, next_state : STATE_TYPE;
process(clk, reset)
begin
if reset = '1' then
current_state <= S0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;All Exercises (12)
3-State Moore
Design simple 3-state Moore machine
4-State Mealy
Implement 4-state Mealy machine
Sequence Detector
Create sequence detector for "1011"
Traffic Light
Design traffic light controller
Vending Machine
Implement vending machine FSM
Elevator Controller
Create elevator controller (3 floors)
UART Receiver FSM
Design UART receiver FSM
One-Hot FSM
Implement one-hot encoded FSM
Door Controller
Create automatic door controller
Washing Machine
Design washing machine controller
FSM Debug
Debug FSM with unreachable states
Mini-Project
Digital safe combination lock
Digital safe combination lock
Topics Covered
- Binary counters
- BCD counters
- Programmable counters
- Timer modules
- Watchdog timers
All Exercises (10)
Binary Counter
Design 4-bit binary up counter
Decade Counter
Implement decade (0-9) counter
Programmable Counter
Create programmable counter (loadable)
Digital Clock
Design 24-hour digital clock
Frequency Divider
Implement frequency divider
PWM Generator
Create PWM generator
Stopwatch
Design stopwatch with lap time
Real-Time Clock
Implement real-time clock (hours, minutes, seconds)
Timeout Timer
Create timeout timer with interrupt
Mini-Project
Kitchen timer with display
Kitchen timer with display
Part 4: Advanced Design Techniques
60 pagesTopics Covered
- ROM implementation
- RAM design (single/dual port)
- FIFO design
- Memory initialization
- Cache concepts
Exercise 10.3: Single Port RAM
type RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
signal RAM : RAM_TYPE := (others => (others => '0'));
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(to_integer(unsigned(addr))) <= data_in;
end if;
data_out <= RAM(to_integer(unsigned(addr)));
end if;
end process;All Exercises (10)
ROM Design
Design 16x8 ROM with constant data
Single Port RAM
Implement 32x16 single port RAM
Dual Port RAM
Create dual port RAM with separate clocks
FIFO with Flags
Design FIFO with almost full/empty flags
LIFO Stack
Implement LIFO (stack) memory
ROM from File
Create ROM from file using TEXTIO
Memory Controller
Design memory controller with wait states
CAM
Implement content addressable memory (CAM)
Byte Enable Memory
Create memory with byte enable
Mini-Project
Cache controller
Cache controller
Topics Covered
- Testbench architecture
- Stimulus generation
- File I/O operations
- Assertions and reporting
- Self-checking testbenches
Exercise 11.4: Self-checking testbench
process
begin
for i in 0 to 15 loop
A <= std_logic_vector(to_unsigned(i, 4));
B <= std_logic_vector(to_unsigned(15-i, 4));
wait for 10 ns;
assert SUM = std_logic_vector(to_unsigned(15, 5))
report "Error at i=" & integer'image(i)
severity error;
end loop;
report "Test complete" severity note;
wait;
end process;All Exercises (12)
Basic Testbench
Create simple testbench for AND gate
Clock Generation
Design testbench with clock generation
File Input
Implement testbench with file input
Self-Checking TB
Create self-checking testbench for adder
Random Stimulus
Design testbench with random stimulus
Coverage Collection
Implement testbench with coverage collection
FSM Testbench
Create testbench for FSM
Multiple Test Cases
Design testbench with multiple test cases
Assertions
Implement testbench with assertions
Memory TB
Create testbench for memory module
Constrained Random
Design constrained random testbench
Mini-Project
Complete test suite for ALU
Complete test suite for ALU
Topics Covered
- Component instantiation
- Generate statements (for-generate, if-generate)
- Configuration declarations
- Top-level design methodology
- Design partitioning
All Exercises (10)
4-Bit Adder
Create 4-bit adder from 1-bit full adders
8-Bit Multiplier
Design 8-bit multiplier using generate
Parameterized Register
Implement parameterized shift register
Hierarchical Processor
Create hierarchical processor design
Multi-Level Hierarchy
Design using multiple levels of hierarchy
Configurable ALU
Implement configurable ALU
Generic Components
Create generic components with parameters
Configuration Statements
Design using configuration statements
Chip-Level Design
Implement chip-level design with pads
Mini-Project
Complete system integration
Complete system integration
Topics Covered
- UART serial communication
- SPI interface
- I2C protocol
- PWM generation
- Handshake protocols
All Exercises (10)
UART Transmitter
Design UART transmitter
UART Receiver
Implement UART receiver
SPI Master
Create SPI master controller
I2C Slave
Design I2C slave device
7-Segment Display
Implement 7-segment display controller
VGA Sync
Create VGA sync generator
PS/2 Keyboard
Design PS/2 keyboard interface
Manchester Encoder
Implement Manchester encoder/decoder
I2S Audio
Create I2S audio interface
Mini-Project
UART loopback with FIFO
UART loopback with FIFO
Topics Covered
- FIR filters
- IIR filters
- Multiply-accumulate (MAC) units
- Digital oscillators
- Signal processing components
All Exercises (8)
FIR Filter
Design 4-tap FIR filter
Moving Average
Implement moving average filter
MAC Unit
Create MAC unit for DSP
DDS
Design direct digital synthesizer (DDS)
CORDIC
Implement CORDIC algorithm (rotation mode)
Noise Generator
Create digital noise generator
LMS Filter
Design adaptive filter LMS algorithm
Mini-Project
Complete audio filter
Complete audio filter
Topics Covered
- 8-bit RISC Processor
- Digital Voltmeter
- Game - Simple Pong
- Music Synthesizer
- Ethernet MAC Layer
All Exercises (1)
Choose 3-4 Projects
Select and complete 3-4 capstone projects from the list below
Learn by Doing
Every concept is reinforced with practical VHDL code examples you can run and modify
1process(clk, reset)2begin3 if reset = '1' then4 Q <= '0';5 elsif rising_edge(clk) then6 if enable = '1' then7 Q <= D;8 end if;9 end if;10end process;Progress Checkpoints
Track your learning journey with clear milestones and skill validations
After Chapter 3
Can design basic combinational circuits
After Chapter 7
Can implement sequential circuits with timing
After Chapter 11
Can create comprehensive testbenches
After Chapter 14
Ready for real-world design projects
Capstone Projects
Apply everything you have learned with these comprehensive real-world projects. Choose 3-4 to complete your learning journey.
8-bit RISC Processor
Design a complete processor with custom instruction set, control unit, datapath integration, and memory interface
Components
- Instruction set design
- Control unit implementation
- Datapath integration
- Memory interface
Digital Voltmeter
Build an ADC interface with display controller, calibration logic, and automatic range selection
Components
- ADC interface
- Display controller
- Calibration logic
- Range selection
Game - Simple Pong
Create a complete game with VGA controller, ball physics engine, paddle control, and score keeping system
Components
- VGA controller
- Ball physics
- Paddle control
- Score keeping
Music Synthesizer
Implement a digital synthesizer with note generation, ADSR envelope shaping, MIDI interface, and audio output
Components
- Note generation
- ADSR envelope
- MIDI interface
- Audio output
Ethernet MAC Layer
Design networking hardware with CRC calculation, frame assembly, flow control, and error detection
Components
- CRC calculation
- Frame assembly
- Flow control
- Error detection
Rust for Automotive Engineers
Learn Rust through real engineering problems: torque calculations, CAN bus, OBD-II, embedded systems. 90+ exercises across 18 weeks. All units in metric (Nm, kg, °C, km/h, kPa).
Engineering Foundations
Learn Rust through mechanical & physics problems
Control Systems
Enums, pattern matching & state machines for automotive control
Embedded Rust Fundamentals
Hardware interfaces, CAN bus & real-time systems
Advanced Embedded Systems
HAL, drivers & production embedded patterns
Production Projects
Build real automotive applications
Build Real Automotive Software
Portfolio projects that solve actual automotive engineering problems - CAN bus, OBD-II, BMS, and more.
CAN Bus Analyzer
IntermediateMonitor and decode live CAN traffic from any vehicle OBD-II port
- Real-time message capture
- DBC file parsing
- Signal decoding to engineering units
- Message filtering and search
- Data logging to CSV
Battery Management System
AdvancedComplete BMS for 12S lithium pack with safety monitoring
- Cell voltage monitoring (2.8-4.2V)
- State of charge estimation
- Temperature protection (max 60°C)
- Passive cell balancing
- CAN reporting interface
OBD-II Scanner
IntermediateRead live data and diagnostic codes from any OBD-II vehicle
- Standard PID requests
- DTC read/clear
- Live data dashboard
- Freeze frame data
- VIN decoding
Engine ECU Simulator
AdvancedSimulate engine ECU for testing dashboards and loggers
- Configurable engine model
- CAN message transmission
- Fault injection
- Load/RPM sweep modes
- OBD-II response simulation
Digital Dashboard
AdvancedReplacement instrument cluster with CAN input
- Speedometer (km/h)
- Tachometer with redline
- Trip computer (L/100km)
- Warning indicator system
- Multi-page display
Vehicle Data Logger
IntermediateHigh-speed logging of vehicle sensors and CAN data
- 100Hz sampling rate
- Ring buffer storage
- Trigger conditions
- SD card export
- GPS integration
Progress Tracking
Track your journey through 175+ exercises + 3-5 major projects
Learning Levels
Beginner Level
Chapters 1-5Intermediate Level
Chapters 6-10Advanced Level
Chapters 11-14Project Level
Chapter 15Exercise Format Details
Each exercise includes these components:
- 1
Problem Statement
Clear description of the task
- 2
Learning Objectives
What skills are practiced
- 3
Specifications
Inputs, outputs, timing requirements
- 4
Hints
Guidance for complex problems (if needed)
- 5
Solution Template
Starter code structure
- 6
Verification Steps
How to test the design
- 7
Challenge Extensions
Optional enhancements
Additional Resources
Everything you need to succeed on your VHDL learning journey