Personal Learning Dashboard • 2026

Master VHDL & Rust Your North Star

A unified roadmap to keep you focused. Hardware meets automotive software. 175+ VHDL exercises and 16 weeks of Rust for automotive engineers.

by daudithemechanic

15
Chapters
Comprehensive curriculum
175+
Exercises
Hands-on practice
5
Capstone Projects
Real-world applications
200+
Pages
In-depth content
4
Skill Levels
Beginner to Advanced
4
Checkpoints
Track your progress

2026 Complete Learning Roadmap

15 chapters, 175+ exercises, and 5 capstone projects - from digital logic fundamentals to advanced VHDL design

Part 1: VHDL Fundamentals

40 pages
Topics Covered
  • Boolean algebra refresher
  • Logic gates and truth tables
  • Combinational vs sequential circuits
  • VHDL history and applications
  • Simulation vs Synthesis concepts
All Exercises (8)
Ex 1.1

Truth Tables

Create truth tables for AND, OR, XOR, NAND, NOR, XNOR gates

Ex 1.2

Boolean Expressions

Derive Boolean expressions from given truth tables

Ex 1.3

Simplification

Simplify Boolean expressions using Boolean algebra

Ex 1.4

2-Input MUX Design

Design a 2-input multiplexer using basic gates

Ex 1.5

Tool Setup

Install GHDL and GTKWave on your system

Ex 1.6

First VHDL File

Write a simple VHDL file that compiles without errors

Ex 1.7

Waveform Diagram

Create a waveform diagram for a 4-input AND gate

Ex 1.8

Fundamentals Quiz

Quiz: 10 multiple choice questions on digital logic fundamentals

Topics Covered
  • Entity-Architecture pair
  • Port declarations and modes (in, out, inout, buffer)
  • STD_LOGIC and STD_LOGIC_VECTOR
  • BIT, BOOLEAN, INTEGER types
  • Constants and signals
Exercise 2.1: Basic Entity Template
entity EXERCISE_2_1 is
    port (
        A, B : in std_logic;
        F    : out std_logic
    );
end EXERCISE_2_1;
All Exercises (10)
Ex 2.1

3-Input AND Gate

Create entity for a 3-input AND gate

Ex 2.2

4-Bit Input Entity

Design entity with 4-bit input and 1-bit output

Ex 2.3

8-Bit Data Bus

Declare signals for an 8-bit data bus

Ex 2.4

Constants

Create constants for clock period and delay values

Ex 2.5

2-Input OR Gate

Write architecture for a 2-input OR gate

Ex 2.6

Bidirectional Port

Design a 4-bit wide entity with bidirectional port

Ex 2.7

Type Conversion

Convert between std_logic_vector and integer types

Ex 2.8

Custom Package

Create a package with custom data types

Ex 2.9

Debug Exercise

Debug given code with 5 syntax errors

Ex 2.10

Data Types Quiz

Quiz on data types and port modes

Topics Covered
  • Simple signal assignment
  • Conditional signal assignment (when/else)
  • Selected signal assignment (with/select)
  • Generate statements
Exercise 3.3: 4-to-1 MUX using when/else
architecture BEHAVIORAL of MUX4 is
begin
    Y <= A when SEL = "00" else
         B when SEL = "01" else
         C when SEL = "10" else
         D;
end BEHAVIORAL;
All Exercises (12)
Ex 3.1

2-to-1 MUX

Implement 2-to-1 MUX using when/else

Ex 3.2

3-to-8 Decoder

Design 3-to-8 decoder with with/select

Ex 3.3

4-to-1 MUX

Create 4-to-1 MUX using conditional assignment

Ex 3.4

Priority Encoder

Implement priority encoder (4-bit to 2-bit)

Ex 3.5

7-Segment Decoder

Design 7-segment decoder for hex digits 0-F

Ex 3.6

Barrel Shifter

Create barrel shifter using concurrent statements

Ex 3.7

Magnitude Comparator

Implement magnitude comparator (2-bit numbers)

Ex 3.8

Parity Generator

Design parity generator (even/odd selection)

Ex 3.9

Generate Statement

Use generate to create array of 8 AND gates

Ex 3.10

ALU Slice

Implement ALU slice with add/subtract operations

Ex 3.11

Debug Concurrent Code

Debug concurrent code (find 3 logical errors)

Ex 3.12

Mini-Project

Design a simple calculator (add/sub/and/or)

Chapter Mini-Project

Design a simple calculator (add/sub/and/or)

Part 2: Combinational Logic Design

45 pages
Topics Covered
  • Process statement structure
  • Sensitivity lists
  • Variable vs Signal assignment
  • If-then-else statements
  • Case statements
Exercise 4.5: Process with variables
process(A, B, C)
    variable temp : std_logic_vector(3 downto 0);
begin
    temp := A & B & C & '1';
    if temp = "1111" then
        OUTPUT <= '1';
    else
        OUTPUT <= '0';
    end if;
end process;
All Exercises (15)
Ex 4.1

D Flip-Flop

Write process for D flip-flop with async reset

Ex 4.2

8-to-1 MUX

Implement 8-to-1 MUX using case statement

Ex 4.3

BCD Converter

Design BCD to excess-3 converter using process

Ex 4.4

Variables Practice

Create process with variables for temporary calculations

Ex 4.5

Timing Comparison

Compare variable vs signal assignment timing

Ex 4.6

Full Adder

Implement full adder using process

Ex 4.7

Gray Code Converter

Design 4-bit binary to gray code converter

Ex 4.8

ALU Design

Create arithmetic logic unit (ALU) with 4 operations

Ex 4.9

Conditional Branches

Write process with multiple conditional branches

Ex 4.10

Look-up Table

Implement look-up table using case statement

Ex 4.11

Sensitivity List Debug

Debug process with incomplete sensitivity list

Ex 4.12

Hamming Encoder

Design Hamming code encoder (7,4)

Ex 4.13

Thermometer Code

Create process for thermometer code converter

Ex 4.14

Booth Multiplier

Implement booth multiplier (4x4 bits)

Ex 4.15

Mini-Project

Simple CPU control unit

Chapter Mini-Project

Simple CPU control unit

Topics Covered
  • Function declaration and usage
  • Procedure definition
  • Pure vs impure functions
  • Parameter modes (in, out, inout)
  • Return statements
Exercise 5.2: Function for parity calculation
function calc_parity(data : std_logic_vector) return std_logic is
    variable parity : std_logic := '0';
begin
    for i in data'range loop
        parity := parity xor data(i);
    end loop;
    return parity;
end function;
All Exercises (10)
Ex 5.1

Integer to Binary

Write function to convert integer to binary vector

Ex 5.2

Parity Function

Create function for even parity calculation

Ex 5.3

Memory Init Procedure

Design procedure to initialize memory array

Ex 5.4

Maximum Function

Implement function for finding maximum of 3 numbers

Ex 5.5

Out Parameters

Create procedure with out parameters

Ex 5.6

CRC Calculation

Write function for CRC calculation (simple)

Ex 5.7

Bit Reversal

Design procedure for bit reversal

Ex 5.8

Function Overload

Implement function overload for different types

Ex 5.9

Reusable Package

Create package with reusable functions

Ex 5.10

Mini-Project

Math operations package

Chapter Mini-Project

Math operations package

Topics Covered
  • Package declaration and body
  • Library and use clauses
  • Standard packages (std_logic_1164, numeric_std)
  • User-defined packages
  • Component declarations
All Exercises (8)
Ex 6.1

Custom Types Package

Create package with custom types and constants

Ex 6.2

Conversion Package

Design package for conversion functions

Ex 6.3

Component Package

Implement package with component declarations

Ex 6.4

Numeric Std Practice

Use numeric_std for arithmetic operations

Ex 6.5

Math Package

Create math package with add/sub/mult functions

Ex 6.6

Testbench Utilities

Design testbench utilities package

Ex 6.7

UART Constants

Implement package for UART constants

Ex 6.8

Mini-Project

Complete design using packages

Chapter Mini-Project

Complete design using packages

Part 3: Sequential Logic Design

55 pages
Topics Covered
  • D, T, JK, SR flip-flops
  • Synchronous vs asynchronous reset
  • Enable signals
  • Register files
  • Clocking methodologies
Exercise 7.3: D-FF with async reset and enable
process(clk, reset)
begin
    if reset = '1' then
        Q <= '0';
    elsif rising_edge(clk) then
        if enable = '1' then
            Q <= D;
        end if;
    end if;
end process;
All Exercises (15)
Ex 7.1

Sync Reset D-FF

Design D flip-flop with synchronous reset

Ex 7.2

T Flip-Flop

Implement T flip-flop from D flip-flop

Ex 7.3

D-FF with Enable

Create D-FF with async reset and enable

Ex 7.4

4-Bit Register

Design 4-bit register with parallel load

Ex 7.5

Universal Shift Register

Implement universal shift register

Ex 7.6

Register File

Create 8-bit register file (4 registers)

Ex 7.7

JK Flip-Flop

Design JK flip-flop with preset and clear

Ex 7.8

Ripple Counter

Implement ripple counter using T flip-flops

Ex 7.9

Tri-State Register

Create register with tri-state output

Ex 7.10

Up/Down Counter

Design synchronous up/down counter

Ex 7.11

Johnson Counter

Implement Johnson counter

Ex 7.12

FIFO Buffer

Create FIFO buffer (4x8 bits)

Ex 7.13

Debounce Circuit

Design debounce circuit for push button

Ex 7.14

Clock Divider

Implement clock divider (divide by 2, 4, 8)

Ex 7.15

Mini-Project

8-bit accumulator

Chapter Mini-Project

8-bit accumulator

Topics Covered
  • Moore vs Mealy machines
  • State encoding (binary, one-hot, gray)
  • FSM design methodology
  • State transition diagrams
  • Output logic
Exercise 8.5: Sequence detector FSM
type STATE_TYPE is (S0, S1, S2, S3, S4);
signal current_state, next_state : STATE_TYPE;

process(clk, reset)
begin
    if reset = '1' then
        current_state <= S0;
    elsif rising_edge(clk) then
        current_state <= next_state;
    end if;
end process;
All Exercises (12)
Ex 8.1

3-State Moore

Design simple 3-state Moore machine

Ex 8.2

4-State Mealy

Implement 4-state Mealy machine

Ex 8.3

Sequence Detector

Create sequence detector for "1011"

Ex 8.4

Traffic Light

Design traffic light controller

Ex 8.5

Vending Machine

Implement vending machine FSM

Ex 8.6

Elevator Controller

Create elevator controller (3 floors)

Ex 8.7

UART Receiver FSM

Design UART receiver FSM

Ex 8.8

One-Hot FSM

Implement one-hot encoded FSM

Ex 8.9

Door Controller

Create automatic door controller

Ex 8.10

Washing Machine

Design washing machine controller

Ex 8.11

FSM Debug

Debug FSM with unreachable states

Ex 8.12

Mini-Project

Digital safe combination lock

Chapter Mini-Project

Digital safe combination lock

Topics Covered
  • Binary counters
  • BCD counters
  • Programmable counters
  • Timer modules
  • Watchdog timers
All Exercises (10)
Ex 9.1

Binary Counter

Design 4-bit binary up counter

Ex 9.2

Decade Counter

Implement decade (0-9) counter

Ex 9.3

Programmable Counter

Create programmable counter (loadable)

Ex 9.4

Digital Clock

Design 24-hour digital clock

Ex 9.5

Frequency Divider

Implement frequency divider

Ex 9.6

PWM Generator

Create PWM generator

Ex 9.7

Stopwatch

Design stopwatch with lap time

Ex 9.8

Real-Time Clock

Implement real-time clock (hours, minutes, seconds)

Ex 9.9

Timeout Timer

Create timeout timer with interrupt

Ex 9.10

Mini-Project

Kitchen timer with display

Chapter Mini-Project

Kitchen timer with display

Part 4: Advanced Design Techniques

60 pages
Topics Covered
  • ROM implementation
  • RAM design (single/dual port)
  • FIFO design
  • Memory initialization
  • Cache concepts
Exercise 10.3: Single Port RAM
type RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
signal RAM : RAM_TYPE := (others => (others => '0'));

process(clk)
begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(unsigned(addr))) <= data_in;
        end if;
        data_out <= RAM(to_integer(unsigned(addr)));
    end if;
end process;
All Exercises (10)
Ex 10.1

ROM Design

Design 16x8 ROM with constant data

Ex 10.2

Single Port RAM

Implement 32x16 single port RAM

Ex 10.3

Dual Port RAM

Create dual port RAM with separate clocks

Ex 10.4

FIFO with Flags

Design FIFO with almost full/empty flags

Ex 10.5

LIFO Stack

Implement LIFO (stack) memory

Ex 10.6

ROM from File

Create ROM from file using TEXTIO

Ex 10.7

Memory Controller

Design memory controller with wait states

Ex 10.8

CAM

Implement content addressable memory (CAM)

Ex 10.9

Byte Enable Memory

Create memory with byte enable

Ex 10.10

Mini-Project

Cache controller

Chapter Mini-Project

Cache controller

Topics Covered
  • Testbench architecture
  • Stimulus generation
  • File I/O operations
  • Assertions and reporting
  • Self-checking testbenches
Exercise 11.4: Self-checking testbench
process
begin
    for i in 0 to 15 loop
        A <= std_logic_vector(to_unsigned(i, 4));
        B <= std_logic_vector(to_unsigned(15-i, 4));
        wait for 10 ns;
        assert SUM = std_logic_vector(to_unsigned(15, 5))
            report "Error at i=" & integer'image(i)
            severity error;
    end loop;
    report "Test complete" severity note;
    wait;
end process;
All Exercises (12)
Ex 11.1

Basic Testbench

Create simple testbench for AND gate

Ex 11.2

Clock Generation

Design testbench with clock generation

Ex 11.3

File Input

Implement testbench with file input

Ex 11.4

Self-Checking TB

Create self-checking testbench for adder

Ex 11.5

Random Stimulus

Design testbench with random stimulus

Ex 11.6

Coverage Collection

Implement testbench with coverage collection

Ex 11.7

FSM Testbench

Create testbench for FSM

Ex 11.8

Multiple Test Cases

Design testbench with multiple test cases

Ex 11.9

Assertions

Implement testbench with assertions

Ex 11.10

Memory TB

Create testbench for memory module

Ex 11.11

Constrained Random

Design constrained random testbench

Ex 11.12

Mini-Project

Complete test suite for ALU

Chapter Mini-Project

Complete test suite for ALU

Topics Covered
  • Component instantiation
  • Generate statements (for-generate, if-generate)
  • Configuration declarations
  • Top-level design methodology
  • Design partitioning
All Exercises (10)
Ex 12.1

4-Bit Adder

Create 4-bit adder from 1-bit full adders

Ex 12.2

8-Bit Multiplier

Design 8-bit multiplier using generate

Ex 12.3

Parameterized Register

Implement parameterized shift register

Ex 12.4

Hierarchical Processor

Create hierarchical processor design

Ex 12.5

Multi-Level Hierarchy

Design using multiple levels of hierarchy

Ex 12.6

Configurable ALU

Implement configurable ALU

Ex 12.7

Generic Components

Create generic components with parameters

Ex 12.8

Configuration Statements

Design using configuration statements

Ex 12.9

Chip-Level Design

Implement chip-level design with pads

Ex 12.10

Mini-Project

Complete system integration

Chapter Mini-Project

Complete system integration

Topics Covered
  • UART serial communication
  • SPI interface
  • I2C protocol
  • PWM generation
  • Handshake protocols
All Exercises (10)
Ex 13.1

UART Transmitter

Design UART transmitter

Ex 13.2

UART Receiver

Implement UART receiver

Ex 13.3

SPI Master

Create SPI master controller

Ex 13.4

I2C Slave

Design I2C slave device

Ex 13.5

7-Segment Display

Implement 7-segment display controller

Ex 13.6

VGA Sync

Create VGA sync generator

Ex 13.7

PS/2 Keyboard

Design PS/2 keyboard interface

Ex 13.8

Manchester Encoder

Implement Manchester encoder/decoder

Ex 13.9

I2S Audio

Create I2S audio interface

Ex 13.10

Mini-Project

UART loopback with FIFO

Chapter Mini-Project

UART loopback with FIFO

Topics Covered
  • FIR filters
  • IIR filters
  • Multiply-accumulate (MAC) units
  • Digital oscillators
  • Signal processing components
All Exercises (8)
Ex 14.1

FIR Filter

Design 4-tap FIR filter

Ex 14.2

Moving Average

Implement moving average filter

Ex 14.3

MAC Unit

Create MAC unit for DSP

Ex 14.4

DDS

Design direct digital synthesizer (DDS)

Ex 14.5

CORDIC

Implement CORDIC algorithm (rotation mode)

Ex 14.6

Noise Generator

Create digital noise generator

Ex 14.7

LMS Filter

Design adaptive filter LMS algorithm

Ex 14.8

Mini-Project

Complete audio filter

Chapter Mini-Project

Complete audio filter

Topics Covered
  • 8-bit RISC Processor
  • Digital Voltmeter
  • Game - Simple Pong
  • Music Synthesizer
  • Ethernet MAC Layer
All Exercises (1)
Ex 15.1

Choose 3-4 Projects

Select and complete 3-4 capstone projects from the list below

Learn by Doing

Every concept is reinforced with practical VHDL code examples you can run and modify

1process(clk, reset)
2begin
3 if reset = '1' then
4 Q <= '0';
5 elsif rising_edge(clk) then
6 if enable = '1' then
7 Q <= D;
8 end if;
9 end if;
10end process;

Progress Checkpoints

Track your learning journey with clear milestones and skill validations

Checkpoint 1

After Chapter 3

Can design basic combinational circuits

Chapters 1-3
Boolean algebraEntity-ArchitectureConcurrent statementsMUX/Decoders
Checkpoint 2

After Chapter 7

Can implement sequential circuits with timing

Chapters 4-7
Process statementsFunctions/ProceduresFlip-flopsRegisters
Checkpoint 3

After Chapter 11

Can create comprehensive testbenches

Chapters 8-11
FSM designCountersMemory designSelf-checking tests
Checkpoint 4

After Chapter 14

Ready for real-world design projects

Chapters 12-14
Hierarchical designCommunication protocolsDSP basics

Capstone Projects

Apply everything you have learned with these comprehensive real-world projects. Choose 3-4 to complete your learning journey.

Project A

8-bit RISC Processor

Design a complete processor with custom instruction set, control unit, datapath integration, and memory interface

Components

  • Instruction set design
  • Control unit implementation
  • Datapath integration
  • Memory interface
Advanced
Project B

Digital Voltmeter

Build an ADC interface with display controller, calibration logic, and automatic range selection

Components

  • ADC interface
  • Display controller
  • Calibration logic
  • Range selection
Intermediate
Project C

Game - Simple Pong

Create a complete game with VGA controller, ball physics engine, paddle control, and score keeping system

Components

  • VGA controller
  • Ball physics
  • Paddle control
  • Score keeping
Advanced
Project D

Music Synthesizer

Implement a digital synthesizer with note generation, ADSR envelope shaping, MIDI interface, and audio output

Components

  • Note generation
  • ADSR envelope
  • MIDI interface
  • Audio output
Advanced
Project E

Ethernet MAC Layer

Design networking hardware with CRC calculation, frame assembly, flow control, and error detection

Components

  • CRC calculation
  • Frame assembly
  • Flow control
  • Error detection
Expert
For Mechanical & Automotive Engineers

Rust for Automotive Engineers

Learn Rust through real engineering problems: torque calculations, CAN bus, OBD-II, embedded systems. 90+ exercises across 18 weeks. All units in metric (Nm, kg, °C, km/h, kPa).

No abstract examples - learn through engine sensors, CAN messages & control systems
Phase 1Weeks 1-4

Engineering Foundations

Learn Rust through mechanical & physics problems

4 weeks
20 exercises
Projects
Variables as sensor readingsMutability for changing measurementsInteger types for counters & signalsFloating-point for precision measurements+1 more
Phase 2Weeks 5-8

Control Systems

Enums, pattern matching & state machines for automotive control

4 weeks
20 exercises
Projects
Enums for discrete statesVariants with dataOption for optional sensorsResult for fallible operations+1 more
Phase 3Weeks 9-12

Embedded Rust Fundamentals

Hardware interfaces, CAN bus & real-time systems

4 weeks
20 exercises
Projects
#![no_std] for bare metalMemory-mapped I/OVolatile access for hardwareBit manipulation+1 more
Phase 4Weeks 13-16

Advanced Embedded Systems

HAL, drivers & production embedded patterns

4 weeks
20 exercises
Projects
embedded-hal traitsGPIO traitsSPI/I2C abstractionsDriver portability+1 more
Phase 5Ongoing

Production Projects

Build real automotive applications

2 weeks
10 exercises
Projects
Cell voltage monitoringState of charge estimationTemperature managementCell balancing algorithms+1 more
Automotive Rust Projects

Build Real Automotive Software

Portfolio projects that solve actual automotive engineering problems - CAN bus, OBD-II, BMS, and more.

CAN Bus Analyzer

Intermediate

Monitor and decode live CAN traffic from any vehicle OBD-II port

  • Real-time message capture
  • DBC file parsing
  • Signal decoding to engineering units
  • Message filtering and search
  • Data logging to CSV

Battery Management System

Advanced

Complete BMS for 12S lithium pack with safety monitoring

  • Cell voltage monitoring (2.8-4.2V)
  • State of charge estimation
  • Temperature protection (max 60°C)
  • Passive cell balancing
  • CAN reporting interface

OBD-II Scanner

Intermediate

Read live data and diagnostic codes from any OBD-II vehicle

  • Standard PID requests
  • DTC read/clear
  • Live data dashboard
  • Freeze frame data
  • VIN decoding

Engine ECU Simulator

Advanced

Simulate engine ECU for testing dashboards and loggers

  • Configurable engine model
  • CAN message transmission
  • Fault injection
  • Load/RPM sweep modes
  • OBD-II response simulation

Digital Dashboard

Advanced

Replacement instrument cluster with CAN input

  • Speedometer (km/h)
  • Tachometer with redline
  • Trip computer (L/100km)
  • Warning indicator system
  • Multi-page display

Vehicle Data Logger

Intermediate

High-speed logging of vehicle sensors and CAN data

  • 100Hz sampling rate
  • Ring buffer storage
  • Trigger conditions
  • SD card export
  • GPS integration

Progress Tracking

Track your journey through 175+ exercises + 3-5 major projects

Learning Levels

Beginner Level

Chapters 1-5
55 exercises

Intermediate Level

Chapters 6-10
70 exercises

Advanced Level

Chapters 11-14
50 exercises

Project Level

Chapter 15
3-5 major projects

Exercise Format Details

Each exercise includes these components:

  • 1

    Problem Statement

    Clear description of the task

  • 2

    Learning Objectives

    What skills are practiced

  • 3

    Specifications

    Inputs, outputs, timing requirements

  • 4

    Hints

    Guidance for complex problems (if needed)

  • 5

    Solution Template

    Starter code structure

  • 6

    Verification Steps

    How to test the design

  • 7

    Challenge Extensions

    Optional enhancements